1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device and, in particular, to a semiconductor device that has a Panel scale Fan-out package structure in which a thin film wiring step and an assembling step are performed on a large panel scale, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
With a demand for the high functionality and miniaturization of electronic equipment in recent years, electronic components have been increasingly integrated and mounted at a higher density. Thus, semiconductor devices used in electronic equipment have been more reduced in size than ever before.
As a method of manufacturing semiconductor devices such as LSI units and IC modules, the following method has been known (see, for example, Japanese Patent Publication No. 2003-197662). First, a plurality of semiconductor chips determined to be nondefective according to an electrical characteristics test is arranged and bonded onto a retention plate in a prescribed arrangement with the element circuit surfaces thereof directed downward. After that, a resin sheet is, for example, arranged on the semiconductor chips and heated and pressed to be molded. Thus, the plurality of semiconductor chips is sealed in a lump by a resin. Next, after the retention plate is separated and the resin sealed body is cut off and processed into a prescribed shape (for example, a circular shape), an insulation material layer is formed on the element circuit surfaces of the semiconductor chips embedded in the resin sealed body. Then, openings are formed in the insulation material layer so as to suit the electrode pads of the semiconductor chips. After that, a wiring layer is formed on the insulation material layer, while conduction portions (via portions) are formed in the openings so as to be connected to the electrode pads of the semiconductor chips. Next, a solder resist layer and solder balls that serve as external electrode terminals are sequentially formed. Then, the semiconductor chips are cut off one by one and segmented into pieces to complete the semiconductor devices.
However, in the conventional semiconductor devices thus obtained, the resin is cured to shrink when the plurality of semiconductor chips is sealed at the same time by the resin and its shrinking amount is not necessarily equal to the designed one. Therefore, after the resin is cured, the semiconductor chips are likely to deviate from designed positions depending on the arrangement positions thereof. In the semiconductor chips in which a positional deviation occurs, the via portions formed in the openings of the insulation material layer and the electrode pads of the semiconductor chips deviate from each other, which results in a problem that the connection reliability is reduced.
Japanese Patent Publication No. 2010-219489 describes a semiconductor device that addresses the problem.
FIG. 20 shows the basic structure of the device.
A semiconductor device 20 has a support plate 1 constituted by a resin cured body or metal. A semiconductor chip 2 is arranged on one principal surface of the support plate 1 with the element circuit surface (front side surface) thereof directed upward, and the surface (rear side surface) opposite to the element circuit surface bonded onto the support plate 1 via an adhesive 3. Further, an insulation material layer 4 is singly formed on the entire principal surface of the support plate 1 so as to cover the element circuit surface of the semiconductor chip 2. A wiring layer 5 made of a conductive metal such as copper is formed on the single insulation material layer 4 and partially withdrawn to the peripheral region of the semiconductor chip 2. In addition, conduction portions (via portions) 6 that electrically connect the electrode pads (not shown) of the semiconductor chip 2 and the wiring layer 5 to each other are formed in the insulation material layer 4 formed on the element circuit surface of the semiconductor chip 2. The conductive portions 6 are formed in a lump to be integrated with the wiring layer 5. Moreover, a plurality of external electrodes 7, such as solder balls, are formed at the prescribed positions of the wiring layer 5. Further, a wiring protection layer (solder resist layer) 8 is formed on the insulation material layer 4 and the wiring layer 5 that does not include the connection parts of the external electrodes 7 such as solder balls.
The device greatly contributes to the high density and the miniaturization of electronic equipment for which the demand has been further increased in recent years.
Meanwhile, it is described in Japanese Patent Publication No. 2010-219489 that a resin cured body made of a cured resin or a flat plate that has a uniform thickness and is made of metal such as stainless steel and a 42 alloy is used as the support plate 1 of the semiconductor device 20. However, the support plate integrated with the semiconductor device plays a role as a product conveyance carrier in a manufacturing step while functioning as a stiffener, a radiation plate, and an electromagnetic shield, and thus a thick stainless steel is generally used to facilitate the handling of a panel, reduce warpage, and facilitate segmentation. This results in the problem that the semiconductor device as a final product is thickened and radiation becomes poor since a material having an excellent heat conduction cannot be selected as a material of the support plate 1. Therefore, it has been difficult to lower the height of (thin) the semiconductor device.
When SUS304 is, for example, used as the support plate (radiation plate) 1, the heat conductivity (16.7 [W/mK]) of the SUS304 is 1/20 or lower than the heat conductivity (about 400 W/mK) of copper generally used as a radiation plate. Therefore, the radiation of the SUS304 is poor, and the effect of reducing PKG heat resistance is small. Further, when a SUS that has a thickness of 0.3 mm is used to reduce the warpage of the support plate, it cannot be applied to a mobile product since its attachment height becomes high.
In addition, it is described in Japanese Patent Publication No. 2010-219489 that the thickness of the semiconductor devices may be reduced by, for example, the mechanical polishing of the surface opposite to the semiconductor-chip mounting surface of the support plate before cutting off and segmenting the semiconductor devices into pieces. However, a specific manufacturing method is not described in Japanese Patent Publication No. 2010-219489, and there are concerns about fluctuations in the polishing and quality reduction due to stress loads to the semiconductor devices. Therefore, it is difficult to put the method of the reduction in the thickness of the semiconductor devices into practical use.